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technical data KK82C55 chmos programmable peripheral interface the integral kk 82c55an is a high-performance, chmos version of the industry standard kk8 2c55an general purpose programmable i/o device wh ich is designed for use with all intel and m o st other m i croprocessors. it provides 24 i/o pins which m a y be individually program m e d in 2 groups of 12 and used in 3 m a jor m odes of operation. in mode 0, each group of 12 i/o pins m a y be progr am m e d in sets of 4 and 8 to be inputs or outputs. in mode 1, each group m a y be program m e d to have 8 lines of input or output. 3 of the rem a ining 4 pins are used for handshaking and inte rrupt control signals. mode 2 is a strobed bi- directional bus configuration. features ? co m p atib le with all in tel an d mo st oth e r micro p r o cesso rs ? hi gh speed, ? z ero w a i t st at e? operat i on wi t h 8m hz 8086/ 88 and 80186/ 188 ? 24 program m a bl e i/ o pi ns ? low power chm o s ? com p letely ttl com p atible ? co n t ro l w o rd read -back cap a b ility ? direct bit set/reset cap a b ility ? 2 . 5 m a dc driv e cap a b ility o n all i/o po rt ou tp u t s ? avai l a bl e i n 40-pi n dip ? av ailab l e in express ? st andard tem p erat ure r a nge ? ext e nded tem p erat ure r a nge ? gro u p a con t ro l dat a bu s bu ff er re a d / wr it e con t ro l logi c gro u p b co nt ro l gro u p b po r t b (8) gr o u p b po r t c low e r (4) gro u p a por t c up p e r (4) gro u p a po r t a (8) pa 7 -p a 0 pc 7 -p c 4 pc 3 -p c 0 pb 7 -p b 0 d 7 -d 0 rd rd wr cs a 1 a 0 re se t 8 bi t in t e r n a l dat a b u s f i gure 1 1. 2. 3. 4. 5. 6. 7. 8. 9. 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pa 4 pa 5 pa 6 pa 7 wr re set d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 v cc pb 7 pb 6 pb 5 pb 4 pb 3 pa 3 pa 2 pa 1 pa 0 rd cs v ss a 1 a 0 pc 7 pc 6 pc 5 pc 4 pc 0 pc 1 pc 2 pc 3 pb 0 pb 1 pb 2 f i gure 2 1 http://www..net/ datasheet pdf - http://www..net/
KK82C55a sy m bol p i n num ber ty pe nam e and funct i on pa 3-0 1-4 i/ o por t a, pins 0-3: lower ni bbl e of an 8-bi t dat a out put l a t c h buffer and an 8-bi t dat a i nput l a t c h. rd 5 i r e ad c ontr o l: thi s i nput i s l o w duri ng c p u read operat i ons. cs 6 i chip select: a low on this i nput enables the 82c55a to respond to r d and wr si gnal s r d and w r are i gnored ot herwi s e. g n d 7 sy st em g r o u n d . a 1-0 8-9 i address: these i nput si gnal s i n conjunct i on r d and wr cont rol t h e sel ect i on of one of t h e t h ree port s or t h e cont rol word regi st ers. a 1 a 0 r d wr cs i nput oper ation ( r ead) 0 0 0 1 0 po rt a - data bu s 0 1 0 1 0 po rt b - data bu s 1 0 0 1 0 po rt c - data bu s 1 1 0 1 0 co n t ro l wo rd - data bu s output oper ation ( w r ite) 0 0 1 0 0 data bu s - po rt a 0 1 1 0 0 data bu s - po rt b 1 0 1 0 0 data bu s - po rt c 1 1 1 0 0 data bus ? contr o l disable function x x x x 1 data bus-3-state x x 1 1 0 data bus-3-state pc 7-4 10-13 i/ o por t c , pins 4-7: upper ni bbl e of an 8-bi t dat a out put l a t c h/ buffer and an 8-bi t dat a i nput buffer (no l a t c h for i nput ). thi s port can be di vi ded i n t o t w o 4-bi t port s under t h e m ode cont rol . each 4-bi t port cont ai ns a 4-bi t l a t c h and i t can be used for t h e cont rol si gnal out put s and st at us si gnal i nput s i n conjunct i on wi t h port s a and b . pc 0-3 14-17 i/ o por t c , pins 0-3: lower ni bbl e of port c . pb 0-7 18-25 i/ o por t b , pins 0-7: an 8-bi t dat a out put l a t c h/ buffer and an 8-bi t dat a i nput buffer vc c 26 system pow e r : +5v power suppl y d 7-0 27-34 i/ o data b u s: b i -di r ect i onal , t r i - st at e dat a bus l i n es, connect ed t o sy st em dat a bus r e set 35 i r e set: a hi gh on t h i s i nput cl ears t h e cont rol regi st er and al l port s are set t o t h e i nput m ode wr 36 i w r ite c ontr o l: thi s i nput i s l o w duri ng c p u wri t e operat i ons pa 7-4 37-40 i/ o por t a pins 4-7: upper ni bbl e of an 8-bi t dat a out put l a t c h/ buffer and an 8-bi t dat a i nput l a t c h 2 http://www..net/ datasheet pdf - http://www..net/
KK82C55a KK82C55an functional description general the kk 82c55an is a programmable periphe ral interface device designed for use in intel microcomputer systems. its function is that of a general purpose i/ o com ponent to interface peripheral equipm ent to the m i crocom puter system bus. the funct i onal confi gurat i on of t h e kk 82c55an is programmed by the system software so that normally no external logic is necessary to interface pe ripheral devices or structures. da ta bus buffer this 3-state bidirectional 8-bit buffer is used to interface the KK82C55an to the sy stem data bus. data is transmitted or received by the buffer upon execution of input or output instructions by the cpu. control words and st atus inform ation are al so t r ansferred t h rough t h e dat a bus buffer. read/ w ri te and control l ogi c the funct i on of t h i s bl ock i s t o m a nage al l of t h e i n t e rnal and ext e rnal t r ansfers of bot h dat a and c ont rol or st at us words. it accepts inputs from the cpu addr ess and control busses and in turn, i ssues com m a nds to both of the control groups. group a and group b controls the functional configuration of each por t is program m e d by the system s softwa re. in essence, the cpu ?outputs? a cont rol word t o t h e kk 82c55an. the control word contains in formation such as ?mode?, ?bit set?, ?bit reset?, etc., that initializes the functional configurati on of the 82c55a. each of the contro l blocks (group a and group b) accepts ?com m a nds? from the read/w rite control logic, receives ?cont rol words? from the internal data bus and issues the proper com m a nds t o i t s associ at ed port s . c ont rol group a - port a and port c upper (c 7 - c 4 ) c ont rol group b - port b and port c l o wer (c 3 - c 0 ) th e co n t ro l wo rd reg i ster can b e b o t h written an d read as sh o w n in th e ad d r ess d eco d e tab l e in th e p i n d e scrip tio n s . fig u r e 6 sh o w s th e co n t ro l wo rd fo rm at fo r b o t h read an d w r ite o p e ratio n s . w h en th e co n t ro l wo rd is read , b it d7 will always b e a lo g i c ?1 ?, as th is im p lies co n t ro l wo rd m o d e in fo rm atio n . ports a, b, and c the kk 82c55an contains three 8-bit ports (a, b, and c). all can be configured in a wide variety of functional characteristics by the system software but each has its own special features or ?persona lity? to further enhance the p o w er an d flex ib ility o f th e kk 82c55an. port a. one 8-bi t dat a out put l a t c h/ buffer and one 8-bi t i nput l a t c h/ buffer. b o t h ?pul l - up? and ?pul l - down? bus hol d devices are present on port a. port b. one 8-bi t dat a i nput / out put l a t c h/ buffer. onl y ?pul l - up? bus hol d devi ces are present on port b . port c. one 8-bi t dat a out put l a t c h/ buffer and one 8-bi t dat a i nput buffer (no l a t c h for i nput ). thi s port can be di vi ded i n t o t w o 4-bi t port s under t h e m ode cont rol . each 4-bi t port cont ai ns a 4-bi t l a t c h and i t can be used for t h e cont rol si gnal out put s and st at us si gnal i nput s i n conjunct i on wi t h por t s a and b . onl y ?pul l - up? bus hol d devi ces are present on port c . see fi gure 4 for t h e bus-hol d ci rcui t confi gurat i on for port a, b , and c . 3 http://www..net/ datasheet pdf - http://www..net/
KK82C55a gro u p a c ont ro l dat a bu s b u ffer re a d / wr it e co nt r o l lo gi c gr o u p b co nt ro l gro u p b po rt b (8 ) gro u p b po rt c lo w e r (4 ) gr o u p a po r t c up p e r (4) gr oup a por t a (8) pa 7 -p a 0 pc 7 -p c 4 pc 3 -p c 0 pb 7 -p b 0 d 7 -d 0 rd rd wr cs a 1 a 0 re set 8 bi t i n t e r nal d a t a bus f i gure 3.kk 82c55an block diagram showing data bus buffer and read write control logic functions reset in te r n a l da ta i n in t e r n a l dat a ou t in te r n a l dat a ou t ex t e rna l po r t a pi n reset in t e r n a l dat a ou t vcc p* wr ex t e rna l po r t b , c pi n * not e: p o r t p i ns lo a d e d w i t h m o r e tha n 2 0 p f c a p a c it an ce m a y n o t ha ve t h e i r lo g i c le ve l g u ar a n te e d fo ll o w i n g a ha r d w a r e r e se t. * wr fig u re 4 . po rt a, b, c, bus-ho ld co nfig ura tio n 4 http://www..net/ datasheet pdf - http://www..net/
KK82C55a kk 82c55an operational description mode selection there are three basic m odes of operation that can be selected by the system software: m ode 0 - b a si c i nput / out put m ode 1 - st robed input / out put m ode 2 - b i -di r ect i onal b u s w h en the reset input goes ?high? all ports will be set to the input m ode with all 24 port lines held at a logic ?one? level by t h e i n t e rnal bus hol d devi ces (see fi gure 4 not e ). aft e r t h e reset i s rem oved t h e kk 82c55an can remain in the input m o d e with n o ad d itio n a l in itializatio n req u i red . th is elim in ates th e n eed fo r p u llu p o r p u lld o w n d e v i ces in ?all cmos? desi gns. duri ng t h e execut i on of t h e sy st em program , any of t h e ot her m odes m a y be sel ect ed by usi ng a si ngl e out put in stru ctio n . th is allo ws a sin g l e kk 82c55an to service a variety of peripheral devices with a simple software m a in ten a n ce ro u tin e. the m odes for port a and port b can be se parat e l y defi ned, whi l e port c i s di vi ded i n t o t w o port i ons as requi red by t h e po rt a an d po rt b d e fin itio n s . all o f th e o u t p u t reg i sters, in clu d i n g th e statu s flip -flo p s , will b e reset wh en ev er th e m ode i s changed. m odes m a y be com b i n ed so t h at t h ei r funct i onal defi ni t i on can be ?t ai l o red? t o al m o st any i/ o st ruct ure. for i n st ance; group b can be program m e d i n m ode 0 t o m oni t o r si m p l e swi t c h cl osi ngs or di spl a y com put at i onal resul t s , group a coul d be program m e d i n m ode 1 t o m oni t o r a key board or t a pe reader on an i n t e rrupt - dri v en basi s. ad r e s s b u s 8 rd, w r d7 - d 0 a 0 , a 1 bc a cont r o l bus da t a bus 8 4 4 8 mode 0 pb 7 -p b 0 pc 3 -p c 0 pc 7 -p c 4 pa 7 -p a 0 8 8 mode 1 pb 7 -p b 0 c ontr o l or i / o co nt r o l or i / o pa 7 -p a 0 bc a 8 8 mode 2 pb 7 -p b 0 i/ o con t r o l pa 7 -p a 0 bc a fig u re 5 . ba sic mo d e definitio ns a n d bus interfa ce 5 http://www..net/ datasheet pdf - http://www..net/
KK82C55a d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 gr o u p b p o rt c ( l ow er) 1 = i n p u t 0 = o u t p ut por t b 1 = i n p u t 0 = o u t p ut mo de se l e ct i o n 0 = mod e 0 1 = mod e 1 gr o u p b p o rt c ( l ow er) 1 = i n p u t 0 = o u t p ut por t b 1 = i n p u t 0 = o u t p ut mo de se l e ct i o n 00 = mo de 0 01 = mo de 1 1 x = m ode 2 mo de se t f l a g 1 = a c ti ve fig u re 6 . mo d e definitio n fo rma t the m ode defi ni t i ons and possi bl e m ode com b i n at i ons m a y s eem confusi ng at fi rst but aft e r a cursory revi ew of t h e com p lete device operation a sim p le, l ogical i/o approach will surface. the design of the 82c55a has taken into account things such as efficient pc boa rd layout, control signal definition vs pc layout and com p lete functional flexibility to support alm o st any periphera l device with no external logic. such design represents the m a xim u m use of the available pins. single bit set/reset feature any of t h e ei ght bi t s of port c can be set or r e set usi ng a si ngl e output i n st ruct i on. thi s feat ure reduces soft ware requi rem e nt s i n c ont rol - based appl i cat i ons. w h en port c i s bei ng used as st at us/ c ont rol for port a or b , t h ese bi t s can be set or reset by usi ng t h e b i t set / r eset operat i on just as i f t h ey were dat a out put port s . d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 bi t s e t / r e s e t 1 = s e t 0 = r e s et bi t s e l e ct 01 234 56 7 01 010 10 1 b 0 00 110 01 1 b 1 00 001 11 1 b 2 b i t s e t / r e s e t f l a g 0 = a c t i v e don? t ca r e fig u re 7 . bit set/reset fo rma t 6 http://www..net/ datasheet pdf - http://www..net/
KK82C55a interrupt control functions w h en t h e kk 82c55an is programmed to operate in mode 1 or m ode 2, control signals are provided that can be used as i n t e rrupt request i nput s t o t h e c p u. the i n t e rrupt request si gnal s , generat e d from port c , can be i nhi bi t e d or enabl e d by set t i ng or reset t i ng t h e associ at ed inte fl i p -fl op, usi ng t h e bi t set / r eset funct i on of port c . thi s funct i on al l o ws t h e program m e r t o di sal l o w or al l o w a speci fi c i/ o devi ce t o i n t e rrupt t h e c p u wi t hout affect i ng any ot her devi ce i n t h e i n t e rrupt st ruct ure. inte fl i p -fl op defi ni t i on: (bit-set) - inte is set - interrupt enable (bit-reset) ? inte is reset - interrupt disable no te: al l m a sk fl i p -fl ops are aut o m a t i cal l y reset duri ng m ode sel ect i on and devi ce r e set . operat i n g m odes mode 0 (basic input/output). this functional configurati on provides sim p le input and output operations for each of th e th ree p o r ts. no ?h an d s h a k i n g ? is req u i red , d a ta is sim p ly written to o r read fro m a sp ecified p o r t. m ode 0 b a si c funct i onal defi ni t i ons: ? two 8-bi t port s and t w o 4-bi t port s . ? any port can be i nput or out put . ? out put s are l a t c hed. ? input s are not l a t c hed. ? 16 di fferent input / o ut put confi gurat i ons are possi bl e i n t h i s m ode. mode 0 (basic input) t rr t ir t hr t ar t ra t rd t df rd in p u t cs , a 1 , a 0 d 7 -d 0 7 http://www..net/ datasheet pdf - http://www..net/
KK82C55a mode 0 (basic output) t ww t dw t wd t wa t aw t wb wr d 7 -d 0 cs ,a 1, a 0 ou t p u t mode 0 port definition a b group a group b d4 d3 d1 d0 port a port c (uppe r) # port b port c (lower) 0 0 0 0 o u t p u t outpu t 0 o u t p u t outpu t 0 0 0 1 o u t p u t outpu t 1 o u t p u t input 0 0 1 0 o u t p u t outpu t 2 i n p u t outpu t 0 0 1 1 o u t p u t outpu t 3 i n p u t i n p u t 0 1 0 0 o u t p u t i n p u t 4 outpu t outpu t 0 1 0 1 o u t p u t i n p u t 5 outpu t input 0 1 1 0 o u t p u t i n p u t 6 i n p u t outpu t 0 1 1 1 o u t p u t i n p u t 7 i n p u t i n p u t 1 0 0 0 i n p u t outpu t 8 o u t p u t outpu t 1 0 0 1 i n p u t outpu t 9 o u t p u t input 1 0 1 0 i n p u t outpu t 1 0 i n p u t outpu t 1 0 1 1 i n p u t outpu t 1 1 i n p u t i n p u t 1 1 0 0 i n p u t i n p u t 1 2 outpu t outpu t 1 1 0 1 i n p u t i n p u t 1 3 outpu t input 1 1 1 0 i n p u t i n p u t 1 4 i n p u t outpu t 1 1 1 1 i n p u t i n p u t 1 5 i n p u t i n p u t 8 http://www..net/ datasheet pdf - http://www..net/
KK82C55a mode 0 configurations co nt ro l w o rd # 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10 0 0 00 0 0 a c? b 8 4 4 8 pa 7 -p a 0 pc 7 -p c 4 pc 3 -p c 0 pb 7 -p b 0 d 7 -d 0 co nt ro l w o rd # 1 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10 0 0 00 0 1 a c? b 8 4 4 8 pa 7 -p a 0 pc 7 -p c 4 pc 3 -p c 0 pb 7 -p b 0 d 7 -d 0 co nt ro l w o rd # 2 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10 0 0 00 1 0 a c? b 8 4 4 8 pa 7 -p a 0 pc 7 -p c 4 pc 3 -p c 0 pb 7 -p b 0 d 7 -d 0 co nt ro l w o rd # 3 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10 0 0 00 1 1 a c? b 8 4 4 8 pa 7 -p a 0 pc 7 -p c 4 pc 3 -p c 0 pb 7 -p b 0 d 7 -d 0 co nt ro l w o rd # 4 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10 0 0 10 0 0 a c? b 8 4 4 8 pa 7 -p a 0 pc 7 -p c 4 pc 3 -p c 0 pb 7 -p b 0 d 7 -d 0 co nt ro l w o rd # 5 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10 0 0 10 0 1 a c? b 8 4 4 8 pa 7 -p a 0 pc 7 -p c 4 pc 3 -p c 0 pb 7 -p b 0 d 7 -d 0 co nt ro l w o rd # 6 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10 0 0 10 1 0 a c? b 8 4 4 8 pa 7 -p a 0 pc 7 -p c 4 pc 3 -p c 0 pb 7 -p b 0 d 7 -d 0 co nt ro l w o rd # 7 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10 0 0 10 1 1 a c? b 8 4 4 8 pa 7 -p a 0 pc 7 -p c 4 pc 3 -p c 0 pb 7 -p b 0 d 7 -d 0 9 http://www..net/ datasheet pdf - http://www..net/
KK82C55a co nt ro l w o rd # 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10 0 1 00 0 0 a c? b 8 4 4 8 pa 7 -p a 0 pc 7 -p c 4 pc 3 -p c 0 pb 7 -p b 0 d 7 -d 0 co nt ro l w o rd # 9 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10 0 1 00 0 1 a c? b 8 4 4 8 pa 7 -p a 0 pc 7 -p c 4 pc 3 -p c 0 pb 7 -p b 0 d 7 -d 0 co nt ro l w o rd # 1 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10 0 1 00 1 0 a c? b 8 4 4 8 pa 7 -p a 0 pc 7 -p c 4 pc 3 -p c 0 pb 7 -p b 0 d 7 -d 0 co nt ro l w o rd # 1 1 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10 0 1 00 1 1 a c? b 8 4 4 8 pa 7 -p a 0 pc 7 -p c 4 pc 3 -p c 0 pb 7 -p b 0 d 7 -d 0 co nt ro l w o rd # 1 2 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10 0 1 10 0 0 a c? b 8 4 4 8 pa 7 -p a 0 pc 7 -p c 4 pc 3 -p c 0 pb 7 -p b 0 d 7 -d 0 co nt ro l w o rd # 1 3 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10 0 1 10 0 1 a c? b 8 4 4 8 pa 7 -p a 0 pc 7 -p c 4 pc 3 -p c 0 pb 7 -p b 0 d 7 -d 0 co nt ro l w o rd # 1 4 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10 0 1 10 1 0 a c? b 8 4 4 8 pa 7 -p a 0 pc 7 -p c 4 pc 3 -p c 0 pb 7 -p b 0 d 7 -d 0 co nt ro l w o rd # 1 5 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10 0 1 10 1 1 a c? b 8 4 4 8 pa 7 -p a 0 pc 7 -p c 4 pc 3 -p c 0 pb 7 -p b 0 d 7 -d 0 10 http://www..net/ datasheet pdf - http://www..net/
KK82C55a operat i n g m odes mode 1 (strobed input/output) . thi s funct i onal confi gurat i on provi des a m eans for t r ansferri ng i/ o dat a t o or from a speci fi ed port i n conjunct i on wi t h st robes or ?handshaki ng? si gnal s . in m ode 1, port a and port b use t h e l i n es on port c to generate or accept these ?handshaking? signals. m ode 1 b a si c funct i onal defi ni t i ons: ? two groups (group a and group b ) . ? each group cont ai ns one 8-bi t dat a port and one 4-bi t cont rol / d at a port . ? the 8-bi t dat a port can be ei t h er i nput or out put ? b o t h i nput s and out put s are l a t c hed. ? the 4-bi t port i s used for cont rol and st at us of t h e ? 8-bi t dat a port . input control signal definition stb (st r obe input ). a ?l ow? on t h i s i nput l o ads dat a i n t o t h e i nput l a t c h. ibf (input buffer full f/f) a ?hi gh? on t h i s out put i ndi cat es t h at t h e dat a has been l o aded i n t o t h e i nput l a t c h; i n essence, an acknowl e dgem e nt . ibf is set b y stb i nput bei ng l o w and i s reset by t h e ri si ng edge of t h e r d i nput . intr (interrupt request) a ?hi gh? on t h i s out put can be used t o i n t e rrupt t h e c p u when an i nput devi ce i s request i ng servi ce. intr i s set by t h e stb is a ?one?, ibf is a ?one? and inte is a ?one?. it i s reset by t h e fal l i ng edge of r d . this procedure allows an i nput devi ce t o request servi ce from t h e c p u by si m p l y st robi ng i t s dat a i n t o t h e port . inte a c ont rol l e d by bi t set / r eset of pc 4 . inte b c ont rol l e d by bi t set / r eset of pc 2 con t ro l w o r d d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10 11 1 / 0 x x x pc 6, 7 1 = in pu t 0 = ou t p ut pa 7 -p a 0 8 pc 4 pc 5 pc 3 in te a pc 6, 7 2 st b a ibf a in t r a rd m o de 1 (p or t a ) c o n t ro l w o rd d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1x x x x 1 1 x pb 7 -p b 0 8 pc 2 pc 1 pc 0 in te b st b b ibf b in t r b rd m ode 1 (p or t b ) f i gure 8. m ode 1 input 11 http://www..net/ datasheet pdf - http://www..net/
KK82C55a t st t si b t si t t rib t rit t ph t ps st b ib f in t r rd in p u t fro m pe r i ph e r a l f i gure 9. m ode 1 (st r obed input ) output control signal definition obf (output buffer full f/f). the obf o u t p u t will g o ?lo w ? to in d i cate th at th e cpu h a s written d a ta o u t to th e specified port. the obf f/f will b e set b y th e risin g ed g e o f th e wr i nput and reset by ack input bei ng l o w. ack (acknowledge input). a ?l ow? on t h i s i nput i n form s t h e kk 82c55an that the data from port a or port b has been accepted. in essence, a response from the peripheral de vice indicating that it has recei ved the data output by the cpu. intr (interrupt request). a ?hi gh? on t h i s out put can be used t o i n t e rrupt t h e c p u when an out put devi ce has accepted data transm itted by th e cpu. intr is set when ack is a ?one?, obf is a ?one? and inte is a ?one?. it is reset by t h e fal l i ng edge of wr . inte a c ont rol l e d by bi t set / r eset of pc 6 . inte b c ont rol l e d by bi t set / r eset of pc 2 . cont ro l w o rd d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10 10 1 / 0 x x x pc 6, 7 1 = i n pu t 0 = out p u t pa 7 -p a 0 8 pc 6 pc 7 pc 3 in te a pc 4, 5 2 ack a ob f a in tr a w r mode 1 ( p ort a ) cont ro l w o rd d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1x x x x1 0x pb 7 -p b 0 8 pc 2 pc 1 pc 0 in te b ack b ob f b int r b w r mode 1 ( p ort b ) f i gure 10. m ode 1 out p ut 12 http://www..net/ datasheet pdf - http://www..net/
KK82C55a t aob t wi t t ak t ai t t wb out p u t ac k in tr obf w r t wo b f i gure 11. m ode 1 (st r obed out p ut ) combi n ati o ns of mode 1 port a and port b can be i ndi vi dual l y defi ned as i nput or out put i n m ode 1 t o support a wi de vari et y of st robed i/ o appl i cat i ons. cont ro l wo r d d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10 1 1 1 / 0 1 0 x pc 6, 7 1 = i n pu t 0 = o u t p u t pa 7 -p a 0 8 pc 4 pc 5 pc 6,7 pb 7 -p b 0 2 st b a ib f a in t r a w r pc 3 pc 1 pc 2 ob f b ac k b in t r b pc 0 8 rd po r t a ? s t r o b e d in pu t p o r t b ? s t r o b e d out p u t cont ro l wo r d d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 10 1 0 1 / 0 1 1 x pc 4, 5 1 = i n pu t 0 = o u t p u t pa 7 -p a 0 8 pc 7 pc 6 pc 4,5 pb 7 -p b 0 ob f a in t r a w r pc 3 pc 2 pc 1 st b b ib f b in t r b pc 0 8 rd p o r t a ? s t rob e d ou t p u t p o rt b ? st ro b e d i n p u t 2 ac k a f i gure 12. c o mbi n at i o ns of m ode 1 operating modes mode 2 (strobed bidirectional bus i/o). thi s funct i onal confi gurat i on provi des a m eans for com m uni cat i ng wi t h a peripheral device or structur e on a single 8-bit bus for both transm itting a nd receiving data (bidirectional bus i/o). ?handshaki ng? si gnal s are provi ded t o m a i n t a i n proper bus fl o w d i scip lin e in a sim ilar m a n n e r to mode 1 . in terru p t generat i on and enabl e / d i s abl e funct i ons are al so avai l a bl e. m ode 2 b a si c funct i onal defi ni t i ons: ? used i n group a onl y . ? one 8-bi t , bi -di r ect i onal bus port (port a) and a 5- bi t cont rol port (port c ) . ? b o t h i nput s and out put s are l a t c hed. ? the 5-bi t cont rol port (port c ) i s used for cont rol and st at us for t h e 8-bi t , bi -di r ect i onal bus port (port a). 13 http://www..net/ datasheet pdf - http://www..net/
KK82C55a bidirectional bus i/o cont rol signal definition intr (interrupt request). a hi gh on t h i s out put can be used t o i n t e rrupt t h e c p u for i nput or out put operat i ons. output operations obf (output buffer full) . the obf o u t p u t will g o ?lo w ? to in d i cate th at th e cpu h a s written d a ta o u t to p o r t a. ack (acknow l edge). a ?l ow? on t h i s i nput enabl e s t h e t r i - st at e out put buffer of port a t o send out t h e dat a . oth e rwise, th e o u t p u t b u ffer will b e in th e h i g h im p e d a n ce state. inte 1 (the inte flip-flop associated with obf ). c ont rol l e d by bi t set / r eset of pc 6 . input operations stb (strobe input). a ?l ow? on t h i s i nput l o ads dat a i n t o t h e i nput l a t c h. ibf (input buffer full f/f) . a ?hi gh? on t h i s out put i ndi cat es t h at dat a has been l o aded i n t o t h e i nput l a t c h. inte 2 (the inte flip-flop associated with ibf). c ont rol l e d by bi t set / r eset of pc 4 . co n t ro l w o rd d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 1 x x x 1 /0 1 / 0 1 /0 pc 2- 0 1 ? in p u t 0 ? ou t p u t po r t b 1 ? in pu t 0 ? o u tpu t g r oup b 1 ? in p u t 0 ? ou t p u t figure 13. mode control word pa 7 -p a 0 pc 6 pc 7 pc 3 in t e 1 pc 2-0 3 ack a obf a in tr a w r pc 5 pc 4 in t e 2 ib f a st b a rd f i gure 14. m ode 2 14 http://www..net/ datasheet pdf - http://www..net/
KK82C55a t wo b t ao b t ak t st t si b t ps t ad t kd t ph t ri b wr ob f ack in t r st b ib f pe ri ph e r a l bus rd da t a f r om c p u t o kk 82c55an da t a f r om pe ri p h era l t o kk 82c55an da ta f r om kk 82c55an to pe ri p h era l da t a f r om kk 82c55an to 8080 fig u re 1 5 . mode 2 (bid irectio na l) note: any sequence where wr occurs before ack , and stb occurs before rd is perm issible. ( wr ack mask obf rd stb mask ibf intr ? ? ? + ? ? ? = ) 15 http://www..net/ datasheet pdf - http://www..net/
KK82C55a cont ro l word d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 11 x x x 0 1 1 / 0 pc 2- 0 1 = i n pu t 0 = out p u t pa 7 -p a 0 8 pc 7 pc 6 pc 2- 0 pb 7 -p b 0 3 ob f a ack a in tr a w r pc 3 pc 4 pc 5 st b a ib f a 8 rd m ode 2 a nd m o de 0 ( i n p u t ) cont ro l word d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 11 x x x 0 0 1 / 0 pc 2- 0 1 = i n pu t 0 = out p u t pa 7 -p a 0 8 pc 7 pc 6 pc 2- 0 pb 7 -p b 0 3 ob f a ac k a in tr a w r pc 3 pc 4 pc 5 st b a ib f a 8 rd m ode 2 a nd m o de 0 ( out p u t ) cont ro l word d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 11 x x x 1 0 x pa 7 -p a 0 8 pc 7 pc 6 pb 7 -p b 0 ob f a ac k a in tr a w r pc 3 pc 4 pc 5 st b a ib f a 8 rd m ode 2 a nd m o de 1 ( out p u t ) pc 1 pc 2 ob f b ack b in tr b pc 0 cont ro l word d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 11 x x x 1 1 x pa 7 -p a 0 8 pc 7 pc 6 pb 7 -p b 0 ob f a ac k a in tr a w r pc 3 pc 4 pc 5 st b a ib f a 8 rd m ode 2 a n d m o de 1 ( i n p u t ) pc 1 pc 2 st b b ib f b in tr b pc 0 f i gure 16. m ode 1/ 4 c o mbi n at i o ns mo d e definitio n summa ry m o d e 0 m o d e 1 m o d e 2 i n o u t i n o u t g r o u p a only pa 0 i n o u t i n o u t ? pa 1 i n o u t i n o u t ? pa 2 i n o u t i n o u t ? pa 3 i n o u t i n o u t ? pa 4 i n o u t i n o u t ? pa 5 i n o u t i n o u t ? pa 6 i n o u t i n o u t ? pa 7 i n o u t i n o u t ? pb 0 i n o u t i n o u t - pb 1 i n o u t i n o u t - pb 2 i n o u t i n o u t - m o d e 0 pb 3 i n o u t i n o u t - o r pb 4 i n o u t i n o u t - m ode1 pb 5 i n o u t i n o u t - o n l y pb 6 i n o u t i n o u t - pb 7 i n o u t i n o u t - pc 0 i n o u t intr b intr b i / 0 pc 1 i n o u t ibf b obf b i / o pc 2 i n o u t stb b ack b i / o pc 3 i n o u t intr a intr a i n t r a pc 4 i n o u t stb a i / o stb a pc 5 i n o u t ibf a i / o ibf a pc 6 i n o u t i / o ack a ack a pc 7 i n o u t i / o obf a obf a 16 http://www..net/ datasheet pdf - http://www..net/
KK82C55a sp ecia l mo d e co mb ina tio n co nsid era tio ns there are several com b inations of m odes possi bl e. for any com b i n at i on, som e or all of the port c lines are used for cont rol or st at us. the rem a i n i ng bi t s are ei t h er i nput s or out put s as defi ned by a ?set m ode? com m a nd. during a read of port c, the state o f all th e po rt c lin es, ex cep t th e ack and stb lines, will be placed on the data bus. in place of the ack and stb lin e states, flag statu s will ap p ear o n th e d a ta b u s in th e pc 2 , pc 4 , and pc 6 bi t posi t i ons as illu strated b y fig u r e 1 8 . through a ?w rite port c? com m a nd, only the port c pins pr ogram m e d as outputs in a mode 0 group can be written. no other pins can be affected by a ?w rite port c? com m a nd, nor can the interrupt en able flags be accessed. to write to any port c out put program m e d as an out put i n a m ode 1 group or t o change an i n t e rrupt enabl e fl ag, t h e ?set / r eset port c b i t ? com m a nd m u st be used. w i t h a ?set / r eset port c b i t ? com m a nd, any port c l i n e program m e d as an out put (i ncl udi ng intr , ib f and obf ) can be written, or an interrupt enable flag can be either set or reset. port c lines program m e d as inputs, including ack and stb lines, associated with port c ar e not affected by a ?set/reset po rt c bit? co m m a n d . w r itin g to th e corresponding port c bit positions of the ack and stb lin es with th e ?set/reset po rt c bit? co m m a n d will affect th e group a and group b interrupt enable fl ags, as illustrated in figure 18. current drive capability any out put on port a, b or c can si nk or source 2.5m a. thi s feat ure al l o ws t h e kk 82c55an to directly drive darl i ngt on t y pe dri v ers and hi gh-vol t a ge di spl a y s t h at requi re such si nk or source current . reading port c status in m ode 0, port c t r ansfers dat a t o or from t h e peri phe ral devi ce. w h en t h e kk 82c55an is programmed to function in modes 1 or 2, port c generates or accepts ?hand-shaking? signals with the peri pheral device. reading the contents of port c allows the program m e r to test or verify the ?sta tus? of each peripheral device and change the program flow accordingly. there is no special instruction to read t h e st at us i n form at i on from port c . a norm a l read operat i on of port c i s execut e d to p e rfo rm th is fu n c tio n . inp u t configur a t ion d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 i/o i /o ibf a int e a int r a int e b ibf b int r b group a g roup b out p u t configur a t ion d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ob f a int e a i/o i /o int r a int e b ob f b int r b group a g roup b f i gure 17a. m ode 1 st at us w o rd f o rmat d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ob f a int e 1 ibf a int e 2 int r a group a g roup b (d ef i n ed by m ode 0 or m ode 1 s e l e k t i o n ) f i gure 17b. m ode 2 st at us w o rd f o rmat 17 http://www..net/ datasheet pdf - http://www..net/
KK82C55a i n te r r up t e n a b l e fla g p o sitio n a lte r n a t e in t e b pc 2 ack b (ou t p u t m ode 1) or s t b b (i n p u t m ode 1) in t e a2 pc 4 st b a ( i n p u t m ode 1 o r m ode 2 ) in t e a1 pc 6 ack a (o u t pu t m ode 1 or m o d e 2) figure 18. interrupt enable flags in modes 1 and 2 absolute maximum ratings* am bient tem p erature under bias 0 o c to + 7 0 o c storage tem p erature - 65 o c t o + 150 o c suppl y vol t a ge - 0.5 t o + 8.0v operat i ng vol t a ge + 4v t o + 7v vol t a ge on any input gnd-2v t o + 6.5v voltage on any output gnd-0.5v to v cc + 0.5v power di ssi pat i on 1w at t notic e: thi s i s a product i on dat a sheet . the speci fi cat i ons are subject t o change wi t hout not i ce. *warn in g: st ressi ng t h e devi ce beyond t h e ?absol ut e ma xi mum rat i ngs? may cause permanent damage. these are stress ratings only. operation bey ond the ?operating conditions? is not recommended and extende d exposure beyond th e ?op e ra tin g co n d itio n s ? ma y a ffect d evice relia b ility. d.c. characteristics t a = 0 o cto70 o c, v cc =+5v 10%, gnd = 0v (t a =-40 o c to +85 o c for extended tem p erature) sy m bol p a r a m e t e r m i n m a x uni t s test c ondi t i o n s v il input low vol t a ge -0.5 0.8 v v ih input hi gh vol t a ge 2.0 v cc v v ol out put low vol t a ge 0.4 v i ol = 2.5m a v oh out put hi gh vol t a ge 3.0 v i oh =-2.5m a v cc - 0.4 v i oh =-100a i il input leakage c u rrent 1 a v in = v cc t o 0v (not e 1) i ofl output float leakage current 10 a in = v cc t o 0v (not e 2) i dar darl i ngt on dri v e c u rrent 2.5 (note 4) m a po rts a,b,c r ext = 500 ? v ext = 1.7v i phl port hold low leakage current + 5 0 + 3 0 0 a v out = 1.0v port a onl y i phh port hold high leakage current - 5 0 - 3 0 0 a v out = 3.0v po rts a,b,c i phlo port hold low overdrive current - 3 5 0 a v out = 0.8v i phho port hold high overdrive current + 3 5 0 a v out = 3.0v i cc v cc suppl y c u rrent 10 m a (not e 3) i ccsb v cc suppl y c u rrent -st a ndby 10 a v cc = 5.5v v in = v cc or gnd port c ondi t i ons if i/p = open/high o/p = open only w ith data bu s = high/low c s = hi gh reset = lo w pure input s = low/high 18 http://www..net/ datasheet pdf - http://www..net/
KK82C55a notes: 1. pins a1, a0, cs, w r , rd, reset 2. data bu s; po rts b, c 3. out put s open. 4. li m i t out put current t o 4.0m a. capacitance t a = 25 o c, v cc = gnd = 0v sy m bol p a r a m e t e r m i n m ax uni t s test c ondi t i o n s c in input c a paci t a nce 10 pf unm easured pi ns c i/o i/o capacitance 20 pf returned to gnd f c = 1m hz(5) note: 5. sam p l e d not 100% t e st ed. a.c. characteristics t a = 0 o to 7 0 o c, v cc = +5v 10%, gnd = 0v t a = -40 o c to +8 5 o c for ext e nded tem p erat ure bus parameters read cy cle sy m b o l p a r a m e ter m i n m a x u n i t s t e s t conditions t ar address stable before rd _ 0 n s t ra address hold time after rd _ 0 n s t rr rd pulse width 1 5 0 n s t rd data delay from rd _ 1 2 0 n s t df rd _ to data floating 1 0 7 5 n s t rv recovery time between rd / wr 2 0 0 n s write cy cle sy m b o l p a r a m e t e r m i n ma x u n i t s t e s t c o n d i t i o n s t aw address stable before wr _ 0 n s t wa address hold tim e after wr _ 2 0 n s port sab 2 0 n s port c t ww wr pul s e w i dt h 100 ns t dw data setup tim e before wr _ 1 0 0 n s t wd data hold tim e after wr _ 3 0 n s port sab 3 0 n s port c 19 http://www..net/ datasheet pdf - http://www..net/
KK82C55a other timings sym b o l p a r a m e t e r min m ax un i t s test conditions t wb wr = 1 t o out put 350 ns t lr peripheral data before rd 0 n s t hr perip h e ral data after rd 0 n s t ak ack pul s e w i dt h 200 ns t st stb pul s e w i dt h 100 ns t ps per. data before stb hi gh 2 0 n s t ph per. data after stb hi gh 5 0 n s t ad ack = 0 t o out put 1 7 5 n s t kd ack = 1 t o out put fl oat 20 250 ns t wo b wr = 1 to obf = 0 150 ns t aob ack = 0 to obf = 1 150 ns t sib stb = 0 t o ib f = 1 150 ns t rib r d = 1 to ibf = 0 1 5 0 n s t rit r d = 0 to intr = 0 2 0 0 n s t sit stb = 1 to intr = 1 1 5 0 n s t ait ack = 1 to intr = 1 1 5 0 n s t wi t wr = 0 to intr = 0 2 0 0 n s see not e 1 t res r e set pul s e w i dt h 500 ns see not e2 note 1. intr_ m a y occur as early as wr _. 2. pulse width of initial reset pulse after power on m u st be at least 50sec. subsequent reset pulses m a y be 500ns m i n i m u m . th e o u t p u t po rts a b o r c m a y g litch lo w d u r in g th e reset p u l se b u t all p o r t p i n s will b e h e ld at a lo g i c ?o n e? lev e l after th e reset p u l se. write timin g a 0-1 ,c s da t a b u s wr t wa t dw t aw t ww t wd 20 http://www..net/ datasheet pdf - http://www..net/
KK82C55a read timing a 0-1 ,c s da t a b u s rd t ra t dr t ar t rr t rd hi g h i m p e da n c e h i gh i m pe d a nc e val i d a.c. testing input, output waveform a.c. testing load circuit 2.4 0.4 5 2. 0 0. 8 2. 0 0. 8 te s t po in t s c l =15 0pf a.c. testing inputs are driven at 2.4v for a logic 1 and 0.45v for a logic 0 timing measurements are made at 2.0v for a logic 1 and 0.8 for a logic 0. a.c. testing load circuit devic e un de r te s t *v ex t is set a t various voltages during te sting to guarantee the spec ification. c l incl udes jig capacitan ce. v ex t * c l = 150pf 21 http://www..net/ datasheet pdf - http://www..net/
KK82C55a 40-p i n p l as ti c d u al -i n - li n e a m a x 6. 35 a mi n 0 . 3 8 mi n 3 . 1 8 ma x 4 . 9 5 mi n 0 . 3 6 ma x 0 . 5 6 mi n 0 . 7 7 ma x 1 . 7 8 mi n 0 . 2 0 ma x 0 . 3 8 m i n 5 0. 30 m a x 5 3. 20 m i n 1 5. 24 m a x 1 5. 87 m i n 1 2. 32 m a x 1 4. 73 e n o m 2. 54 e 2 n o m 1 5. 24 mi n 2 . 9 2 ma x 5 . 0 8 mi n 0 o ma x 1 0 o l d i m e ns i on, m m a 2 b b 2 c d e e 1 22 http://www..net/ datasheet pdf - http://www..net/

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